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rev. 1.1 9/11 copyright ? 2011 by silicon laboratori es si8640/41/42/45 si8640/41/42/45 l ow -p ower q uad -c hannel d igital i solator features applications safety regulatory approvals description silicon lab's family of ultra-low-power digital isolators are cmos devices offering substantial data rate, propagation delay, power, size, reliability, and external bom advantages over legacy isolation technologies. the operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performance. all device versions have schmitt trigger inputs for high noise immunity and only require vdd bypass capacitors. data rates up to 150 mbps are supported, and all devices achieve propagation delays of less than 10 ns. enable inputs provide a single point control for enabling and disabling output drive. ordering options include a choice of isolation ratings (3.75 and 5 kv) and a selectable fail-safe operating mode to control the default output state dur ing power loss. all products >1 kv rms are safety certified by ul, csa, and vd e, and products in wide-body packages support reinforced insulation withstanding up to 5 kv rms . ? high-speed operation ?? dc to 150 mbps ? no start-up initialization required ? wide operating supply voltage ?? 2.5?5.5 v ? up to 5000 v rms isolation ? 60-year life at rated working voltage ? high electromagnetic immunity ? ultra low power (typical) 5 v operation ?? 1.6 ma per channel at 1 mbps ?? 5.5 ma per channel at 100 mbps 2.5 v operation ?? 1.5 ma per channel at 1 mbps ?? 3.5 ma per channel at 100 mbps ? tri-state outputs with enable ? schmitt trigger inputs ? selectable fail-safe mode ?? default high or low output (ordering option) ? precise timing (typical) ?? 10 ns propagation delay ?? 1.5 ns pulse width distortion ?? 0.5 ns channel-channel skew ?? 2 ns propagation delay skew ?? 5 ns minimum pulse width ? transient immunity 50 kv/s ? aec-q100 qualification ? wide temperature range ?? ?40 to 125 c ? rohs-compliant packages ?? soic-16 wide body ?? soic-16 narrow body ?? qsop-16 ? industrial auto mation systems ? medical electronics ? hybrid electric vehicles ? isolated switch mode supplies ? isolated adc, dac ? motor control ? power inverters ? communications systems ? ul 1577 recognized ?? up to 5000 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1, 60601-1 (reinforced insulation ) ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) ?? en60950-1 (reinforced insulation) ordering information: see page 26.
2 rev. 1.1 si8640/41/42/45
rev. 1.1 3 si8640/41/42/45 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2. eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 3. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2. undervoltage lo ckout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4. fail-safe operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5. typical performance char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. package outline: 16-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. land pattern: 16-pin wide-b ody soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8. package outline: 16-pi n narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9. land pattern: 16-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10. package outline: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11. land pattern: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12. top marking: 16-pin wide b ody soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 12.1. 16-pin wide body soic top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 12.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13. top marking: 16-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.1. 16-pin narrow body so ic top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.2. top marking explana ti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. top marking: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14.1. 16-pin qsop top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4 rev. 1.1 si8640/41/42/45 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature* t a 150 mbps, 15 pf, 5 v ?40 25 125 oc supply voltage v dd1 2.5 ? 5.5 v v dd2 2.5 ? 5.5 v *note: the maximum ambient temperature is dependent on data freque ncy, output loading, number of operating channels, and supply voltage. table 2. electrical characteristics (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdduv? v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd negative-going lockout hysteresis vdd hys 50 70 95 mv positive-going input threshold vt+ all inputs rising 1.4 1.67 1.9 v negative-going input threshold vt? all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?5 0? ? enable input high current i enh v enx =v ih ?2 . 0? a enable input low current i enl v enx =v il ?2 . 0? a notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
rev. 1.1 5 si8640/41/42/45 dc supply current (all inputs 0 v or at supply) si8640bx, ex, si8645bx v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) ? ? ? ? 1.0 2.4 6.1 2.5 1.6 3.8 9.2 4.0 ma si8641bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) ? ? ? ? 1.4 2.3 5.2 3.6 2.2 3.7 7.8 5.4 ma si8642bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) ? ? ? ? 1.8 1.8 4.4 4.4 2.9 2.9 6.6 6.6 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 ? ? 3.6 2.9 5.0 4.0 ma si8641bx, ex v dd1 v dd2 ? ? 3.4 3.3 4.8 4.6 ma si8642bx, ex v dd1 v dd2 ? ? 3.3 3.3 4.6 4.6 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 ? ? 3.6 4.0 5.0 5.6 ma si8641bx, ex v dd1 v dd2 ? ? 3.7 4.1 5.2 5.8 ma si8642bx, ex v dd1 v dd2 ? ? 3.9 3.9 5.4 5.4 ma table 2. electrical characteristics (continued) (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
6 rev. 1.1 si8640/41/42/45 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 ? ? 3.6 17.5 5.0 22.8 ma si8641bx, ex v dd1 v dd2 ? ? 7.3 14.3 9.8 18.5 ma si8642bx, ex v dd1 v dd2 ? ? 11 11 14.3 14.3 ma timing characteristics si864xbx, ex maximum data rate 0 ? 150 mbps minimum pulse width ? ? 5.0 ns propagation delay t phl , t plh see figure 2 5.0 8.0 13 ns pulse width distortion |t plh ? t phl | pwd see figure 2 ? 0.2 4.5 ns propagation delay skew 2 t psk(p-p) ?2 . 04 . 5n s channel-channel skew t psk ?0 . 42 . 5n s all models output rise time t r c l =15pf see figure 2 ? 2.5 4.0 ns output fall time t f c l =15pf see figure 2 ? 2.5 4.0 ns peak eye diagram jitter t jit(pk) see figure 7 ? 350 ? ps common mode transient immunity cmti v i =v dd or 0 v 35 50 ? kv/s enable to data valid t en1 see figure 1 ? 6.0 11 ns enable to data tri-state t en2 see figure 1 ? 8.0 12 ns startup time 3 t su ?1 54 0 s table 2. electrical characteristics (continued) (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
rev. 1.1 7 si8640/41/42/45 figure 1. enable timing diagram figure 2. propagation delay timing enable outputs t en1 t en2 typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v
8 rev. 1.1 si8640/41/42/45 table 3. electrical characteristics (v dd1 =3.3v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdduv? v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd negative-going lockout hysteresis vdd hys 50 70 95 mv positive-going input threshold vt+ all inputs rising 1.4 1.67 1.9 v negative-going input threshold v t? all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 3.1 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?5 0? ? enable input high current i enh v enx =v ih ?2 . 0? a enable input low current i enl v enx =v il ?2 . 0? a dc supply current (all inputs 0 v or at supply) si8640bx, ex, si8645bx v dd1 v dd2 v dd1 v dd2 v i =0(bx), 1(ex) v i =0(bx), 1(ex) v i =1(bx), 0(ex) v i =1(bx), 0(ex) ? ? ? ? 1.0 2.4 6.1 2.5 1.6 3.8 9.2 4.0 ma si8641bx, ex v dd1 v dd2 v dd1 v dd2 v i =0(bx), 1(ex) v i =0(bx), 1(ex) v i =1(bx), 0(ex) v i =1(bx), 0(ex) ? ? ? ? 1.4 2.3 5.2 3.6 2.2 3.7 7.8 5.4 ma si8642bx, ex v dd1 v dd2 v dd1 v dd2 v i =0(bx), 1(ex) v i =0(bx), 1(ex) v i =1(bx), 0(ex) v i =1(bx), 0(ex) ? ? ? ? 1.8 1.8 4.4 4.4 2.9 2.9 6.6 6.6 ma notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation dela y times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. start-up time is the time period from the appl ication of power to valid data at the output.
rev. 1.1 9 si8640/41/42/45 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 ? ? 3.6 2.9 5.0 4.0 ma si8641bx, ex v dd1 v dd2 ? ? 3.4 3.3 4.8 4.6 ma si8642bx, ex v dd1 v dd2 ? ? 3.3 3.3 4.6 4.6 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 ? ? 3.6 3.4 5.0 4.7 ma si8641bx, ex v dd1 v dd2 ? ? 3.5 3.6 4.9 5.1 ma si8642bx, ex v dd1 v dd2 ? ? 3.6 3.6 5.0 5.0 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 ? ? 3.6 12.3 5.0 15.9 ma si8641bx, ex v dd1 v dd2 ? ? 5.9 10.3 7.9 13.4 ma si8642bx, ex v dd1 v dd2 ? ? 8.2 8.2 10.7 10.7 ma table 3. electrical characteristics (continued) (v dd1 =3.3v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation dela y times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. start-up time is the time period from the appl ication of power to valid data at the output.
10 rev. 1.1 si8640/41/42/45 timing characteristics si864xbx, ex maximum data rate 0 ? 150 mbps minimum pulse width ? ? 5.0 ns propagation delay t phl , t plh see figure 2 5.0 8.0 13 ns pulse width distortion |t plh ? t phl | pwd see figure 2 ? 0.2 4.5 ns propagation delay skew 2 t psk(p-p) ?2 . 04 . 5n s channel-channel skew t psk ?0 . 42 . 5n s all models output rise time t r c l =15pf see figure 2 ? 2.5 4.0 ns output fall time t f c l =15pf see figure 2 ? 2.5 4.0 ns peak eye diagram jitter t jit(pk) see figure 7 ? 350 ? ps common mode transient immunity at logic low output cmti v i =v dd or 0 v 35 50 ? kv/s enable to data valid t en1 see figure 1 ? 6.0 11 ns enable to data tri-state t en2 see figure 1 ? 8.0 12 ns startup time 3 t su ?1 54 0 s table 3. electrical characteristics (continued) (v dd1 =3.3v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation dela y times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. start-up time is the time period from the appl ication of power to valid data at the output.
rev. 1.1 11 si8640/41/42/45 table 4. electrical characteristics (v dd1 =2.5v 5%, v dd2 = 2.5 v 5%, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdduv? v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd negative-going lockout hysteresis vdd hys 50 70 95 mv positive-going input threshold vt+ all inputs rising 1.4 1.67 1.9 v negative-going input threshold v t? all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 , v dd2 ?0.4 2.3 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?5 0? ? enable input high current i enh v enx =v ih ?2 . 0? a enable input low current i enl v enx =v il ?2 . 0? a dc supply current (all inputs 0 v or at supply) si8640bx, ex, si8645bx v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) ? ? ? ? 1.0 2.4 6.1 2.5 1.6 3.8 9.2 4.0 ma si8641bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) ? ? ? ? 1.4 2.3 5.2 3.6 2.2 3.7 7.8 5.4 ma si8642bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) ? ? ? ? 1.8 1.8 4.4 4.4 2.9 2.9 6.6 6.6 ma 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
12 rev. 1.1 si8640/41/42/45 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 ? ? 3.6 2.9 5.0 4.0 ma si8641bx, ex v dd1 v dd2 ? ? 3.4 3.3 4.8 4.6 ma si8642bx, ex v dd1 v dd2 ? ? 3.3 3.3 4.6 4.6 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8640bx, si8645bx v dd1 v dd2 ? ? 3.6 3.1 5.0 4.3 ma si8641bx, ex v dd1 v dd2 ? ? 3.5 3.4 4.8 4.8 ma si8642bx, ex v dd1 v dd2 ? ? 3.4 3.4 4.8 4.8 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 ? ? 3.6 9.9 5.0 12.8 ma si8641bx, ex v dd1 v dd2 ? ? 5.2 8.5 7.0 11.1 ma si8642bx, ex v dd1 v dd2 ? ? 6.9 6.9 9.0 9.0 ma table 4. electrical characteristics (continued) (v dd1 =2.5v 5%, v dd2 = 2.5 v 5%, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
rev. 1.1 13 si8640/41/42/45 timing characteristics si864xbx, ex maximum data rate 0 ? 150 mbps minimum pulse width ? ? 5.0 ns propagation delay t phl , t plh see figure 2 5.0 8.0 14 ns pulse width distortion |t plh ? t phl | pwd see figure 2 ? 0.2 5.0 ns propagation delay skew 2 t psk(p-p) ?2 . 05 . 0n s channel-channel skew t psk ?0 . 42 . 5n s all models output rise time t r c l =15pf see figure 2 ? 2.5 4.0 ns output fall time t f c l =15pf see figure 2 ? 2.5 4.0 ns peak eye diagram jitter t jit(pk) see figure 7 ? 350 ? ps common mode transient immunity at logic low output cmti v i =v dd or 0 v 35 50 ? kv/s enable to data valid t en1 see figure 1 ? 6.0 11 ns enable to data tri-state t en2 see figure 1 ? 8.0 12 ns startup time 3 t su ?1 54 0 s table 4. electrical characteristics (continued) (v dd1 =2.5v 5%, v dd2 = 2.5 v 5%, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
14 rev. 1.1 si8640/41/42/45 table 5. regulatory information* csa the si864x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. 60601-1: up to 125 v rms reinforced insulation working voltage; up to 380 v rms basic insulation working voltage. vde the si864x is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. 60747-5-2: up to 1200 v peak for basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. ul the si864x is certified under ul15 77 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. *note: regulatory certifications apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see "5. ordering guide" on page 26. table 6. insulation and safety-related specifications parameter symbol test condition value unit wb soic-16 nb soic-16 qsop-16 nominal air gap (clearance) 1 l(io1) 8.0 4.9 3.6 mm nominal external tracking (creepage) 1 l(io2) 8.0 4.01 3.6 mm minimum internal gap (internal clearance) 0.014 0.011 0.008 mm tracking resistance (proof tracking index) pti iec60112 600 600 600 v rms erosion depth ed 0.019 0.019 0.031 mm resistance (input-output) 2 r io 10 12 10 12 10 12 ? capacitance (input-output) 2 c io f = 1 mhz 2.0 2.0 2.0 pf input capacitance 3 c i 4.0 4.0 4.0 pf notes: 1. the values in this table correspond to the nominal creep age and clearance values. vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic-16 and qsop-16 packages and 8.5 mm minimum for the wb soic-16 package. ul does not impose a clearance and cr eepage minimum for component -level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic-16, 3.6 mm for qsop-16 packages and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si86xx is converted into a 2-terminal device. pins 1?8 are shorted together to form the first terminal and pins 9?16 are shorted together to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground.
rev. 1.1 15 si8640/41/42/45 table 7. iec 60664-1 (vde 0844 part 2) ratings parameter test conditions specification nb soic-16 wb soic-16 basic isolation group material group i i installation classification rated mains voltages < 150 v rms i-iv i-iv rated mains voltages < 300 v rms i-iii i-iv rated mains voltages < 400 v rms i-ii i-iii rated mains voltages < 600 v rms i-ii i-iii table 8. iec 60747-5-2 insulation characteristics for si86xxxx* parameter symbol test condition characteristic unit wb soic-16 nb soic-16 maximum working insulation voltage v iorm 1200 630 vpeak input to output test voltage v pr method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 2250 1182 transient overvoltage v iotm t = 60 sec 6000 6000 vpeak pollution degree (din vde 0110, table 1) 22 insulation resistance at t s , v io =500v r s >10 9 >10 9 ? *note: maintenance of the safety data is ensu red by protective circuits. the si86xxxx provides a climate classification of 40/125/21. table 9. iec safety limiting values 1 parameter symbol test condition min typ max unit wb soic-16 nb soic-16 case temperature t s ? ? 150 150 c safety input, output, or supply current i s ? ja = 100 c/w (wb soic-16), 105 c/w (nb soic-16, qsop-16), v i = 5.5 v, t j =150c, t a =25c ? ? 220 210 ma device power dissipation 2 p d ? ? 275 275 mw notes: 1. maximum value allowed in the event of a failure; also see the thermal derating curve in figures 3 and 4. 2. the si86xx is tested with vdd1 = vdd2 = 5.5 v, tj = 150 oc , cl = 15 pf, input a 150 mbps 50% duty cycle square wave.
16 rev. 1.1 si8640/41/42/45 figure 3. (wb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 4. (nb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 10. thermal characteristics parameter symbol test condition wb soic-16 nb soic-16 qsop-16 unit ic junction-to-air thermal resistance ? ja 100 105 oc/w 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 450 300 370 220 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 430 300 360 210 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v
rev. 1.1 17 si8640/41/42/45 table 11. absolute maximum ratings 1 parameter symbol min typ max unit storage temperature 2 t stg ?65 ? 150 oc ambient temperature under bias t a ?40 ? 125 oc supply voltage v dd1 , v dd2 ?0.5 ? 7.0 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive channel i o ??10ma lead solder temperature (10 s) ? ? 260 oc maximum isolation (input to output) (1 sec) nb soic-16, qsop-16 ? ? 4500 v rms maximum isolation (input to output) (1 sec) wb soic-16 ? ? 6500 v rms notes: 1. permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the oper ational sections of this data sheet. exposure to absolute maximum ratings for extended periods may degrade performance. 2. vde certifies storage temper ature from ?40 to 150 c.
18 rev. 1.1 si8640/41/42/45 2. functional description 2.1. theory of operation the operation of an si864x channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si864x channel is shown in figure 5. figure 5. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 6 for more details. figure 6. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
rev. 1.1 19 si8640/41/42/45 2.2. eye diagram figure 7 illustrates an eye-diagram take n on an si8640. for the data source, the test used an anritsu (mp1763c) pulse pattern generator set to 1000 ns/div. the output of the generator's clock and data from an si8640 were captured on an oscillosc ope. the results illustra te that data integrity was mainta ined even at the high data rate of 150 mbps. the results also show that 2 ns pulse wid th distortion and 350 ps peak jitter were exhibited. figure 7. eye diagram
20 rev. 1.1 si8640/41/42/45 3. device operation device behavior during start-up, normal operation, an d shutdown is shown in figu re 8, where uvlo+ and uvlo- are the positive-going and negative-going thresholds resp ectively. refer to table 12 to determine outputs when power supply (vdd) is not present. additionally, refer to table 13 for logic conditions when enable pins are used. table 12. si86xx logic operation v i input 1,2 en input 1,2,3,4 vddi state 1,5,6 vddo state 1,5,6 v o output 1,2 comments hh or nc p p h enabled, normal operation. lh or nc p p l x 7 l p p hi-z 8 disabled. x 7 h or nc up p l 9 h 9 upon transition of vddi from unpowered to pow- ered, v o returns to the same state as v i in less than 1 s. x 7 l up p hi-z 8 disabled. x 7 x 7 p up undetermined upon transition of vddo from unpowered to pow- ered, v o returns to the same state as v i within 1 s, if en is in either the h or nc state. upon transition of vddo from unpowered to powered, v o returns to hi-z within 1 s if en is l. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. en is the enable control input located on the same output side. 2. x = not applicable; h = logic high; l = logic low; hi-z = high impedance. 3. it is recommended that the enable inputs be connected to an external logic high or low level when the si86xx is operating in noisy environments. 4. no connect (nc) replaces en1 on si8640/45. no connect replaces en2 on the si8645. no connects are not internally connected and can be left floating, tied to vdd, or tied to gnd. 5. ?powered? state (p) is defined as 2.5 v < vdd < 5.5 v. 6. ?unpowered? state (up) is defined as vdd = 0 v. 7. note that an i/o can power the die for a given side through an internal diode if its source has adequate current. 8. when using the enable pin (en) function, t he output pin state is driven into a hi gh-impedance state when the en pin is disabled (en = 0). 9. see "5. ordering guide" on page 26 for details. this is the selectable fail-safe operating mode (ordering option). some devices have default output state = h, and some have default output state = l, depending on the ordering part number (opn). for default high devices, the data channels have pull-ups on inputs/outputs. for default low devices, the data channels have pull-downs on inputs/outputs.
rev. 1.1 21 si8640/41/42/45 table 13. enable input truth 1 p/n en1 1,2 en2 1,2 operation si8640 ? h outputs b1, b2, b3, b4 are enabled and follow the input state. ? l outputs b1, b2, b3, b4 are disabled and in high impedance state. 3 si8641 h x output a4 enabled and follows the input state. l x output a4 disabled and in high impedance state. 3 x h outputs b1, b2, b3 are enabled and follow the input state. x l outputs b1, b2, b3 are disabled and in high impedance state. 3 si8642 h x outputs a3 and a4 are enabled and follow the input state. l x outputs a3 and a4 are disabled and in high impedance state. 3 x h outputs b1 and b2 are enabled and follow the input state. x l outputs b1 and b2 are disabled and in high impedance state. 3 si8645 ? ? outputs b1, b2, b3, b4 are enabled and follow the input state. notes: 1. enable inputs en1 and en2 can be used for multiplexing, fo r clock sync, or other output control. en1, en2 logic operation is summarized for each isolator product in table 13. these inputs are internally pulled-up to local vdd by a 2 a current source allowing them to be con nected to an external logic level (high or low) or left floating. to minimize noise coupling, do not connect circuit traces to en1 or en2 if they are left floating. if en1, en2 are unused, it is recommended they be connected to an external logic level, es pecially if the si86xx is operating in a noisy environment. 2. x = not applicable; h = logic high; l = logic low. 3. when using the enable pin (en) function, the output pin state is driven into a high-impedance state when the en pin is disabled (en = 0).
22 rev. 1.1 si8640/41/42/45 3.1. device startup outputs are held low during powerup until vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs. 3.2. undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. both side a and side b each have their own undervoltage lockout monitors. each side can enter or exit uvlo independently. for example, side a unconditionally enters uvlo when v dd1 falls below v dd1(uvlo?) and exits uvlo when v dd1 rises above v dd1(uvlo+) . side b operates the same as side a with respect to its v dd2 supply. figure 8. device behavior during normal operation input v dd1 uvlo- v dd2 uvlo+ uvlo- uvlo+ output tstart tstart tstart tphl tplh tsd
rev. 1.1 23 si8640/41/42/45 3.3. layout recommendations to ensure safety in the end us er application, high voltage circ uits (i.e., circuits with >30 v ac ) must be physically separated from the safety extra-low voltage circuits (selv is a circuit with <30 v ac ) by a certain distance (creepage/clearance). if a component, su ch as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). table 5 on page 14 and table 6 on page 14 detail the working voltage and creepage/clearan ce capabilities of the si86xx. thes e tables also detail the component standards (ul1577, iec60747, csa 5a), which are readily accepted by certif ication bodies to provide proof for end-system specifications requirements. refer to t he end-system specification (6 1010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 3.3.1. supply bypass the si864x family requires a 0.1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. to enhance the robustness of a design, it is further recommended that the user also add 1 f bypass capacitors and include 100 ? resistors in series with the inputs and outputs if the system is excessively noisy. 3.3.2. pin connections for narrow-body devices, pin 2 and pin 8 gnd must be externally connected to respec tive ground. pin 9 and pin 15 must also be connected to external ground. no conn ect pins are not internally connected. they can be left floating, tied to vdd, or tied to gnd. 3.3.3. output pin termination the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled impedance pcb traces. 3.4. fail-saf e operating mode si86xx devices feature a selectable (by ordering option ) mode whereby the default ou tput state (when the input supply is unpowered) can either be a logic high or logi c low when the output supply is powered. see table 12 on page 20 and "5. ordering guide" on page 26 for more information.
24 rev. 1.1 si8640/41/42/45 3.5. typical perfor mance characteristics the typical performance characteristics de picted in the following diagrams are for information purposes only. refer to tables 2, 3, and 4 for actual specification limits. figure 9. si8640/45 typical v dd1 supply current vs. data rate 5, 3.3, and 2.5 v operation figure 10. si8641 typical v dd1 supply current vs. data rate 5, 3.3, and 2.5 v operation figure 11. si8642 typical v dd1 or v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 12. si8640/45 typical v dd2 supply current vs. data rate 5, 3.3, and 2.5 v figure 13. si8641 typical v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 14. propagation delay vs. temperature 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 5.0 6.0 7.0 8.0 9.0 10.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120 delay (ns) temperature (degrees c)
rev. 1.1 25 si8640/41/42/45 4. pin descriptions name soic-16 pin# type description v dd1 1 supply side 1 power supply. gnd1 2 ground side 1 ground. a1 3 digital input side 1 digital input. a2 4 digital input side 1 digital input. a3 5 digital i/o side 1 digital input or output. a4 6 digital i/o side 1 digital input or output. en1/nc* 7 digital input side 1 active high enable. nc on si8640/45. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. en2/nc* 10 digital input side 2 active high enable. nc on si8645. b4 11 digital i/o side 2 digital input or output. b3 12 digital i/o side 2 digital input or output. b2 13 digital output side 2 digital output. b1 14 digital output side 2 digital output. gnd2 15 ground side 2 ground. v dd2 16 supply side 2 power supply. *note: no connect. these pins are not internally connected. they can be left floating, tied to v dd or tied to gnd. v dd1 gnd1 a1 a3 a4 en1 gnd1 a2 v dd2 gnd2 b2 b1 b4 b3 gnd2 en2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8641 v dd1 gnd1 a1 a3 a4 nc gnd1 a2 v dd2 gnd2 b2 b1 b4 b3 gnd2 en2/nc i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8640/45 v dd1 gnd1 a1 a3 a4 en1 gnd1 a2 v dd2 gnd2 b2 b1 b4 b3 gnd2 en2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8642
26 rev. 1.1 si8640/41/42/45 5. ordering guide revision b devices are recommended for all new designs. table 14. ordering guide for valid opns 1 ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side max data rate (mbps) default output state isolation rating (kv) temp (c) package revision b devices 2,3 si8640bc-b-is1 4 0 150 low 3.75 ?40 to 125 c nb soic-16 si8640ec-b-is1 4 0 150 high 3.75 ?40 to 125 c nb soic-16 si8641bc-b-is1 3 1 150 low 3.75 ?40 to 125 c nb soic-16 si8641ec-b-is1 3 1 150 high 3.75 ?40 to 125 c nb soic-16 si8642bc-b-is1 2 2 150 low 3.75 ?40 to 125 c nb soic-16 si8642ec-b-is1 2 2 150 high 3.75 ?40 to 125 c nb soic-16 SI8645BC-B-IS1 4 0 150 low 3.75 ?40 to 125 c nb soic-16 si8640bd-b-is 4 0 150 low 5.0 ?40 to 125 c wb soic-16 si8640ed-b-is 4 0 150 high 5.0 ?40 to 125 c wb soic-16 si8641bd-b-is 3 1 150 low 5.0 ?40 to 125 c wb soic-16 si8641ed-b-is 3 1 150 high 5.0 ?40 to 125 c wb soic-16 si8642bd-b-is 2 2 150 low 5.0 ?40 to 125 c wb soic-16 si8642ed-b-is 2 2 150 high 5.0 ?40 to 125 c wb soic-16 si8645bd-b-is 4 0 150 low 5.0 ?40 to 125 c wb soic-16 notes: 1. all packages are rohs-compliant. moisture sensitivity level is msl3 for wide-body soic-16, narrow-body soic-16, and qsop-16 packages with peak reflow temperatures of 260 c according to the jedec industry standard classifications a nd peak solder temperatures. 2. revision a devices are supported for existing designs, but revision b is recommended for all new designs. 3. all devices >1 kv rms are aec-q100 qualified.
rev. 1.1 27 si8640/41/42/45 revision a devices 2,3 si8640bc-a-is1 4 0 150 low 3.75 ?40 to 125 c nb soic-16 si8640ec-a-is1 4 0 150 high 3.75 ?40 to 125 c nb soic-16 si8641bc-a-is1 3 1 150 low 3.75 ?40 to 125 c nb soic-16 si8641ec-a-is1 3 1 150 high 3.75 ?40 to 125 c nb soic-16 si8642bc-a-is1 2 2 150 low 3.75 ?40 to 125 c nb soic-16 si8642ec-a-is1 2 2 150 high 3.75 ?40 to 125 c nb soic-16 si8642ba-a-iu 2 2 150 low 1.0 ?40 to 125 c qsop-16 si8645ba-a-iu 4 0 150 low 1.0 ?40 to 125 c qsop-16 si8641ba-a-iu 3 1 150 low 1.0 ?40 to 125 c qsop-16 si8645bc-a-is1 4 0 150 low 3.75 ?40 to 125 c nb soic-16 si8640bd-a-is 4 0 150 low 5.0 ?40 to 125 c wb soic-16 si8640ed-a-is 4 0 150 high 5.0 ?40 to 125 c wb soic-16 si8641bd-a-is 3 1 150 low 5.0 ?40 to 125 c wb soic-16 si8641ed-a-is 3 1 150 high 5.0 ?40 to 125 c wb soic-16 si8642bd-a-is 2 2 150 low 5.0 ?40 to 125 c wb soic-16 si8642ed-a-is 2 2 150 high 5.0 ?40 to 125 c wb soic-16 si8645bd-a-is 4 0 150 low 5.0 ?40 to 125 c wb soic-16 table 14. ordering guide for valid opns 1 (continued) ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side max data rate (mbps) default output state isolation rating (kv) temp (c) package notes: 1. all packages are rohs-compliant. moisture sensitivity level is msl3 for wide-body soic-16, narrow-body soic-16, and qsop-16 packages with peak reflow temperatures of 260 c according to the jedec industry standard classifications a nd peak solder temperatures. 2. revision a devices are supported for existing designs, but revision b is recommended for all new designs. 3. all devices >1 kv rms are aec-q100 qualified.
28 rev. 1.1 si8640/41/42/45 6. package outline: 16-pin wide body soic figure 15 illustrates the package details for the si864x digital isolator. ta ble 15 lists the values for the dimensions shown in the illustration. figure 15. 16-pin wide body soic table 15. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.1 0.3 d 10.3 bsc e 10.3 bsc e1 7.5 bsc b 0.31 0.51 c 0.20 0.33 e 1.27 bsc h 0.25 0.75 l 0.4 1.27 ? 0 7
rev. 1.1 29 si8640/41/42/45 7. land pattern: 16-pin wide-body soic figure 16 illustrates the reco mmended land pattern details for the si864x in a 16-p in wide-body soic. table 16 lists the values for the dimens ions shown in the illustration. figure 16. 16-pin soic land pattern table 16. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
30 rev. 1.1 si8640/41/42/45 8. package outline: 16 -pin narrow body soic figure 17 illustrates the package details for the si864x in a 16-pin narrow-body soic (so-16). table 17 lists the values for the di mensions shown in the illustration. figure 17. 16-pin small outline integrated circuit (soic) package table 17. package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b0 . 3 10 . 5 1 c0 . 1 70 . 2 5 d 9.90 bsc e 6.00 bsc e1 3.90 bsc e 1.27 bsc l0 . 4 01 . 2 7 l2 0.25 bsc
rev. 1.1 31 si8640/41/42/45 h0 . 2 50 . 5 0 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. table 17. package diagram dimensions (continued) dimension min max
32 rev. 1.1 si8640/41/42/45 9. land pattern: 16-pin narrow body soic figure 18 illustrates the recommended land pattern details for the si864x in a 16-pin narrow-body soic. table 18 lists the values for the dimens ions shown in the illustration. figure 18. 16-pin narrow body soic pcb land pattern table 18. 16-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
rev. 1.1 33 si8640/41/42/45 10. package out line: 16-pin qsop figure 19 illustrates the package details for the si864 x in a 16-pin qsop package. ta ble 19 lists the values for the dimensions shown in the illustration. figure 19. 16-pin qsop package table 19. package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b 0.20 0.30 c 0.17 0.25 d 4.89 bsc e 6.00 bsc e1 3.90 bsc e 0.635 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 ?
34 rev. 1.1 si8640/41/42/45 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-137, variation ab. 4. recommended card reflow profile is per the jedec/ipc j-std-020d specification for small body components. table 19. package diagram dimensions (continued) dimension min max
rev. 1.1 35 si8640/41/42/45 11. land pattern: 16-pin qsop figure 20 illustrates the recommended land pattern details for the si864x in a 16-pin narrow-body soic. table 20 lists the values for the dimens ions shown in the illustration. figure 20. 16-pin qsop pcb land pattern table 20. 16-pin qsop land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 0.635 x1 pad width 0.40 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern sop63p602x173-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05mm is assumed. ?
36 rev. 1.1 si8640/41/42/45 12. top marking: 16-pin wide body soic 12.1. 16-pin wide b ody soic top marking 12.2. top marking explanation line 1 marking: base part number ordering options (see ordering guide for more information). si86 = isolator product series xy = channel configuration x = # of data channels (4, 3, 2, 1) y = # of reverse channels (2, 1, 0)* s = speed grade (max data rate) and operating mode: a = 1 mbps (default output = low) b = 150 mbps (default output = low) d = 1 mbps (default output = high) e = 150 mbps (default output = high) v = insulation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv; d = 5.0 kv line 2 marking: yy = year ww = workweek assigned by assembly subcontractor. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly house line 3 marking: circle = 1.5 mm diameter (center-justified) ?e3? pb-free symbol country of origin iso code abbreviation tw = taiwan *note: si8645 has 0 reverse channels. si86xysv yywwtttttt tw e3
rev. 1.1 37 si8640/41/42/45 13. top marking: 16-pin narrow body soic 13.1. 16-pin narrow body soic top marking 13.2. top marking explanation line 1 marking: base part number ordering options (see ordering guide for more information). si86 = isolator product series xy = channel configuration x = # of data channels (4, 3, 2, 1) y = # of reverse channels (2, 1, 0)* s = speed grade (max data rate) and operating mode: a = 1 mbps (default output = low) b = 150 mbps (default output = low) d = 1 mbps (default output = high) e = 150 mbps (default output = high) v = insulation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv line 2 marking: circle = 1.2 mm diameter ?e3? pb-free symbol yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. circle = 1.2 mm diameter ?e3? pb-free symbol. *note: si8645 has 0 reverse channels. si86xysv yywwtttttt e3
38 rev. 1.1 si8640/41/42/45 14. top marking: 16-pin qsop 14.1. 16-pin qsop top marking 14.2. top marking explanation line 1 marking: base part number ordering options (see ordering guide for more information). si86 = isolator product series xy = channel configuration x = # of data channels (4, 3, 2, 1) y = # of reverse channels (2, 1, 0)* s = speed grade (max data rate) and operating mode: a = 1 mbps (default output = low) b = 150 mbps (default output = low) d = 1 mbps (default output = high) e = 150 mbps (default output = high) v = insulation rating a=1kv; b=2.5kv; c=3.75kv line 2 marking: circle = 1.2 mm diameter ?e3? pb-free symbol yy = year ww = work week assigned by the assembly hous e. corresponds to the year and work week of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. circle = 1.2 mm diameter ?e3? pb-free symbol. *note: si8645 has 0 reverse channels. si86xysv yywwtttttt e3
rev. 1.1 39 si8640/41/42/45 d ocument c hange l ist revision 0.1 to revision 0.2 ? added chip graphics on page 1. ? moved tables 1 and 11 to page 17. ? updated table 6, ?insulation and safety-related specifications,? on page 14. ? updated table 8, ?iec 60747-5-2 insulation characteristics for si86xxxx*,? on page 15. ? moved table 12 to page 20. ? moved table 13 to page 21. ? moved ?typical performance characteristics? to page 24. ? updated "4. pin descriptions" on page 25. ? updated "5. ordering guide" on page 26. revision 0.2 to revision 1.0 ? reordered spec tables to conform to new convention. ? removed ?pending? throughout document. revision 1.0 to revision 1.1 ? updated high level output voltage voh to 3.1 v in table 3, ?electrical characteristics,? on page 8. ? updated high level output voltage voh to 2.3 v in table 4, ?electrical characteristics,? on page 11.
40 rev. 1.1 si8640/41/42/45 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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